The present invention is directed to multi-voltage domain integrated circuits and, more particularly, to a single power supply level shifter for a multi-voltage domain integrated circuit.
A technique commonly used in complex semiconductor devices to achieve improved speed, power, and reliability is to have two or more power supply voltage domains. Logic signals are conveyed from one voltage domain to another using a level shifter at a boundary between the domains. The level shifter converts the voltage level of a high logic state signal from one voltage domain to a voltage suitable for the destination voltage domain. The voltage level of a low logic state signal is typically the same (ground, for example). A complex semiconductor device such as a system on a chip (SoC) may have many level shifters, so it is important that the power consumption of the level shifters themselves be reduced so that they do not penalize the power savings obtained by using multiple voltage domains.
A conventional level shifter may require two stages to fully level convert a logic signal. A first stage is supplied with the supply voltage from one domain and a second stage is supplied with the supply voltage from the other domain. However, using a level conversion circuit supplied with two power supply voltages causes routing congestion at the boundary between the two voltage domains so a single power supply level shifter is preferable. Moreover, a single supply level shifter can often use a single well, whereas a conventional double power supply level shifter requires different, physically isolated wells for the two power supply domains (double-height layout) penalizing die area.
Accordingly, it would be desirable to have a single power supply level shifter with reduced power consumption.